The inventions described and/or claimed in this patent relate in general to fabricating a capacitor of a semiconductor device; and, more particularly, to a method for fabricating a TaON or Ta2O5 capacitor.
As the integration density of semiconductor devices increases, the size of a memory cell, which stores 1-bit of information, decreases. However, it is a problem to reduce the size of a capacitor without changing its capacitance value and compromising its ability to act as needed to protect from soft error and to maintain a stable operation. The size of a conventional capacitor cannot be reduced in proportion to the reduction of cell size. Accordingly, efforts have been made to find ways to provide the value of capacitance required in a smaller cell. Some of these efforts have focused on reducing the thickness of a dielectric layer of the capacitor, increasing an effective area of the capacitor and a using materials having high dielectric constant. When considering the materials having high dielectric constant, a SiO2 layer is conventionally used as a dielectric layer in the capacitor and also a NO (Nitride-Oxide) layer or an ONO (Oxide-Nitride-Oxide) layer, which has a dielectric constant that is two times as high as that of the SiO2 layer. However, since the SiO2, NO and ONO layers have the low dielectric constant, high capacitance is not expected even if the surface area of the layer is made wider and the thickness of the layer is reduced. (Ba, Sr)TiO3 (hereinafter, referred to as BST), (Pb, Zr)TiO3 (hereinafter, referred to as PZT) and Ta2O5 are used as dielectric materials instead of the conventional dielectric materials. The dielectric constant of the Ta2O5 layer is three times (about 20 to 25) that of the silicon nitride and the Ta2O5 layer is easily etched, compared with the BST layer or the PZT layer. Also, when the Ta2O5 dielectric layer is deposited by the chemical vapor deposition (CVD), a good characteristic of step coverage is expected. Recently, a TaON layer has been developed to improve an unstable stoichiometry of the Ta2O5 layer.
Selection of electrode materials, in the capacitor using the high dielectric constant materials, largely affects characteristics of ferroelectric layer so that, in case of using Ta2O5 layer as a dielectric material, a capacitor having a MIS (Metal-Insulator-Silicon) structure is used instead of a conventional NO (Nitride-Oxide) capacitor. A plate electrode, which is a top electrode of a Ta2O5 capacitor, is a stacked structure of polysilicon/TiN or polysilicon/WN. A storage electrode, which is a bottom electrode, is a polysilicon of which the surface is thermally treated by the rapid thermal nitration (RTN) method.
The thickness of the Ta2O5 ferroelectric layer has to be reduced to obtain the desired capacitance according to integration of semiconductor devices. In order to reduce the thickness of the Ta2O5 ferroelectric layer, a post-thermal treatment is important after forming the capacitor. Even if it is not apparent how much the thickness of Ta2O5 ferroelectric layer may be reduced, the limit thickness is about 20 xc3x85 to 30 xc3x85. If the thickness is reduced, there may be a problem of leakage current increasing.
In an effort to solve the problem described above, the thickness of the ferroelectric layer has been reduced by using metal materials as a bottom electrode. Since the polysilicon layer is used as a bottom electrode in the Ta2O5 capacitor having a MIS structure, a thickness of effective oxide layer (Tox) becomes much larger when a thermal treatment is performed so that a desired capacitance, which is necessary for an operation of highly integrated semiconductor device, is limited. Accordingly, as a metal storage node is used instead of the polysilicon storage node, a generation of an oxide layer is protected so that the thickness of Ta2O5 layer is reduced. However, when metal materials are used as a bottom electrode, there is a problem in that a leakage current of the MIM (Metal-Insulator-Metal) Ta2O5 capacitor increases. Namely, the thickness of effective oxide layer may be reduced to 30 xc3x85 by using the metal storage electrode in the Ta2O5 capacitor having the MIM structure. However, a stable layer is not formed due to a surface reaction of the Ta2O5 ferroelectric layer and the metal bottom electrode so that it is difficult to guarantee a good leakage current characteristic and to be applied in a manufacture of semiconductor device. When the capacitor electrode is formed with a metal layer, a reaction of the metal layer and the polysilicon layer used as a conductive plug or a silicon layer in a substrate has to be prevented and a diffusion barrier layer has to be essentially formed to protect an oxygen diffusion when the ferroelectric layer is deposited.
When, in the MIM structure, a Ru layer is used as a metal bottom electrode, a low pressure chemical deposition (LPCVD) method is used as a deposition method. However, when the Ru layer is deposited by the LPCVD method, a surface of the Ru layer is uneven and oxygen atoms remain in the Ru layer so that the leakage current is increased and the remaining oxygen atoms oxidize a TiN layer, which is used as a barrier metal layer, and then causes the film to lift off. Accordingly, it is, also, difficult to be applied in a highly integrated semiconductor device.
An approach to solve this problem is to deposit a seed layer by the physical vapor deposition (PVD) method before the Ru layer is deposited and then Ru is deposited by the LPCVD method so that surface roughness is improved. However, there are disadvantages in that processes are complex and the step coverage becomes inferior.
The inventions described herein provide methods for fabricating a ferroelectric capacitor having a two steps Ru bottom electrode in order to improve a surface roughness and a current leakage characteristic thereof in a semiconductor device.
In accordance with an aspect of the inventions, there is provided a method for fabricating a capacitor in a semiconductor device. A semiconductor substrate is provided. A bottom electrode is formed by sequentially depositing Ru through a PECVD process (hereinafter, referred to PECVD-Ru) and Ru through a LPCVD process (hereinafter, referred to LPCVD-Ru) on the semiconductor substrate. A Ta2O5 dielectric layer is formed on the bottom electrode. Finally a top electrode is formed on the Ta2O5 dielectric layer.
In accordance with another aspect of the inventions, there is provided a method for fabricating a semiconductor device. A semiconductor substrate is provided. A first interlayer insulating layer is formed. This insulating layer has a contact hole on the semiconductor substrate. A contact plug is formed with conductive materials in the contact hole. A second interlayer insulating layer is formed on the contact plug and the first interlayer insulating layer. A storage node hole is formed by selectively etching the second interlayer insulating layer. A bottom electrode is formed by sequentially depositing Ru in order of a PECVD technique and a LPCVD technique. A dielectric layer is formed on the bottom electrode. A top electrode is formed on the dielectric layer.